The present invention relates to a voltage comparator for comparing a reference voltage with a comparison voltage using field effect transistors.
Conventionally, as a voltage comparator for comparing a reference voltage with a comparison voltage using field effect transistors (FETs), a positive feedback type voltage comparator as shown in FIG. 7 has been proposed (e.g., Japanese Patent Laid-Open No. 7-154216). Referring to FIG. 7, a voltage comparator 201 is constructed by PMOS (P-channel Metal Oxide Semiconductor) field effect transistors T52 to T56, NMOS (N-channel Metal Oxide Semiconductor) field effect transistor T51, and inverters I51 to I54. The PMOS and NMOS field effect transistors will be simply referred to as "transistors" hereinafter unless otherwise specified.
The inverter I51 is formed from an NMOS transistor T61 and PMOS transistor T62. The inverter I52 is formed from an NMOS transistor T71 and PMOS transistor T72.
The power supply terminal of the inverter I51 is connected to that of the inverter I52. The transistor T51 is connected between the connection point of these power supply terminals and a power supply terminal 215 of a power supply voltage VDD. The ground terminal of the inverter I51 is connected to that of the inverter I52. The transistor T56 is connected between the connection point of these ground terminals and a ground terminal 216 of a ground voltage GND.
The output terminal of the inverter I51 is connected to an input terminal A of the inverter I52. The output terminal of the inverter I52 is connected to an input terminal B of the inverter I51. The inverters I51 and I52 construct a positive feedback circuit. The output terminal of the inverter I52 corresponds to an output terminal Vout of the positive feedback type voltage comparator 201.
The transistors T52 and T53 are series-connected between the input terminal A of the inverter I52 and the ground terminal 216. The gate of the transistor T52 corresponds to an input terminal 211 of a comparison voltage Vin.
The transistors T54 and T55 are connected between the input terminal B of the inverter I51 and the ground terminal 216. The gate of the transistor T54 corresponds to an input terminal 212 of a reference voltage Vref.
The input of the inverter I53 is connected to the input terminal A of the inverter I52. The output of the inverter I53 is connected to the gate of the transistor T53. The input of the inverter I54 is connected to the input terminal B of the inverter I51. The output of the inverter I54 is connected to the gate of the transistor T55.
In the voltage comparator 201 having such circuit arrangement, first, complementary control signals CLp and CLn are controlled to turn off the transistors T51 and T56, respectively. No current flows to the transistors T61, T62, T71, and T72, and the input terminals A and B are in the floating state. In the comparison operation, potentials for turning on the transistors T52 and T54 are supplied to the comparison voltage Vin and reference voltage Vref. For this reason, the input terminals A and B are discharged to the ground voltage GND via the transistors T52, T53, T54, and T55.
Next, the complementary control signals CLp and CLn are controlled to turn on the transistors T51 and T56, respectively. A current flows to the transistors T61, T62, T71, and T72, and the inverters I51 and I52 are rendered operative. This forms the positive feedback path of the positive feedback circuit comprising the inverters I51 and I52.
Immediately after the positive feedback path is formed, both the input terminals A and B are at the ground potential GND. Of the input terminals A and B, one having a higher ON resistance for the transistor T52 or T54 is set at the power supply potential VDD, and the other having a lower ON resistance is set at the ground potential GND. When the transistors T52 and T54 are NMOS transistors, as shown in FIG. 7, the ON resistance is in inverse proportion to the gate voltage. The relationship in magnitude between the ON resistances is equivalent to that between the comparison voltage Vin and reference voltage Vref. Hence, the comparison voltage Vin and reference voltage Vref can be compared with each other.
If potentials due to the previous comparison operation remain at the input terminals A and B, the comparison voltage Vin or reference voltage Vref input for the next voltage comparison has an error, and accurate voltage comparison is impossible. To prevent this, when voltage comparison is to be continuously performed, the voltage comparator 201 turns off the transistors T51 and T56 by controlling the control signals CLp and CLn to sufficiently discharge the input terminals A and B to the ground potential GND and then starts the next voltage comparison.
In this case, when the transistors T51 and T56 are turned off, charges stored in the line capacitances of the input terminals A and B are removed via the transistors T52, T53, T54, and T55. However, the ON resistances of the transistors T52 and T54 change depending on the values of the comparison voltage Vin and reference voltage Vref. When the ON resistances are high to some extent, a long time is required to reduce the potentials at the input terminals A and B to the ground potential GND to prepare for the next comparison operation. Hence, the comparison operation cannot be repeated at a high speed.